To fully enable modern applications, such as deep machine learning, interconnections between different dies within a package or different chips on a printed circuit board system need to transmit signals at rates of tens of gigabits per second per lane within an energy footprint of a picojoule per bit. The channel loss at such high frequencies introduces inter-symbol interference (ISI) that limits the communication speed and compensation techniques that are needed conventionally require more power.
When ground-referenced signaling is used, the channel loss may be mild for short connection lengths, however the electrostatic discharge (ESD) circuits and redistribution layer (RDL) interconnect routes present a large parasitic capacitance and degrade the bandwidth (BW) at both the transmitter and receiver ends of the connection. The resulting accumulated loss may be significant and require additional equalization capacity.
For the high-speed links of graphics processing unit (GPU) applications, the channel loss for transmitting one data set at 12.5 GHz is estimated to be 25.3 dB with severe supply noise. To transmit data over the channel at 25 Gbps with a reasonable bit error rate (usually <10−12), all available equalization schemes, such as transmitter pre-emphasis, multi-stage receiver continuous time linear equalization (CTLE) and multi-tap receiver decision feedback equalizer (DFE), are required, increasing both design complexity and power consumption. There is a need for addressing these issues and/or other issues associated with the prior art.